Stress and Reliability for 3D Interconnects: A Material and Processing Perspective

As silicon technology continues to advance beyond the 14 nm technology node, significant challenges have emerged in chip design, materials, and processing. The needs for technology development, especially the growing demand for mobile computing, have generated great interests in the industry to develop 3D integrated circuits (3DICs). Cu through-silicon vias (TSVs) are used to provide short vertical interconnects between stacked dies to reduce the wiring delay, power dissipation, and form factor of the integrated system. While the advantages of 3D integration have been recognized for more than a decade, significant challenges still remain to be addressed, in particular the thermo-mechanical reliability of the TSV structure. The mismatch in the coefficient of thermal expansion between the Cu vias and Si can induce complex stresses in and around the TSV during fabrication, testing, and service to cause serious yield and reliability issues.

This presentation will first analyze the material and processing limits confronting the development of future on-chip interconnects. The effect of thermal stresses on the reliability of TSV structures for 3DICs will be discussed. This is followed by a review of recent results in characterization of thermal stresses for Cu TSV structures using substrate curvature measurement, micro-Raman spectroscopy, and synchrotron x-ray microdiffraction together with finite element analysis. The stress effect on device keep-out zone and the effect of Cu microstructure on stress and reliability, focusing on the mechanism of via extrusion, will be discussed. Potential approaches based on materials, processing, and design optimization to develop reliable TSV structures for 3D interconnects will be explored. The presentation will be concluded with a discussion on applications beyond 3DICs, where microstructure, interface, and processing play important roles in controlling the performance and reliability of devices.